High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip [electronic resource] /
By: Wang, Zheng [author.].
Contributor(s): Chattopadhyay, Anupam [author.] | SpringerLink (Online service).
Series: Computer Architecture and Design Methodologies: Publisher: Singapore : Springer Singapore : Imprint: Springer, 2018Edition: 1st ed. 2018.Description: XX, 197 p. 104 illus., 72 illus. in color. | Binding - Card Paper |.Content type: text Media type: computer Carrier type: online resourceISBN: 9789811010736.Subject(s): EXTC Engineering
| Performance and Reliability | Electronic Circuits and DevicesDDC classification: 621.3815 Online resources: Click here to access eBook in Springer Nature platform. (Within Campus only.)
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Springer Nature eBookSummary: This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. .
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This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. .
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